A typical display screen may be thought of as containing a grid consisting of rows and columns of pixels. The refresh memory used with such a system may be typically thought of as arranged in an addressable array of corresponding rows and columns with a memory location corresponding to each display pixel.
It has been found that for a display having a very large pixel grid, e.g. 1024.times.1024, a very high rate of memory operation is needed in order to provide the required refresh rate for a visually desirable display system. It has also been found that for a large number of display applications the display is primarily line segments which may be thought of as vectors and, in turn, that a substantial number of these vectors are either vertical or horizontal. In order to optimize the writing and refresh rate of a display, a significant consideration is the ability to write and refresh vertical and horizontal vectors. The standard display memory refresh organization allows for a sufficiently rapid horizontal vector read out but this same organization, by optimizing horizontal read out, imposes penalties on vertical writing and read out which make the writing of vertical vectors a limiting factor. Therefore, it would be desirable to have a memory organization which optimizes vertical vector writing and refresh to a rate comparable to that of horizontal vector writing and refresh.
To be more specific, computer graphics display devices which use the raster scan technique require a refresh memory comprising one or more data bits per pixel (picture element) to modulate the intensity of the display beam(s) while the required image is displayed repetitively in a manner similar to that used in the common television receiver. Because this intensity modulation data must be presented to the cathode ray tube in real time, very high data transmission speeds are required. For example, a 1024.times.1024 pixel display requires over one million bits of data per display frame to generate a binary monochrome picture. The minimum acceptable display rates are 30 FPS (frames per second) if display half-frames are interlaced, or 60 FPS for non-interlaced displays, requiring display rates of 30 or 60 megabits per second, respectively. Of course, displays providing multiple levels of intensity or multiple colors require much more beam modulation data in the same amount of time, resulting in data rates as high as 2.5 billion bits per second.
Because it is not desirable to support such transmission speeds in a serial fashion, refresh memories are invariably organized to provide parallel access to several data bits at a time, reducing the memory speed requirements to more practical dimensions. Thus, using conventional memory organization techniques, it is possible to read and/or write several bits in parallel in one refresh memory dimension, but access to several bits in the other dimension requires separate memory cycles.
Raster scan displays are refreshed in a consistent rectangular pattern, making parallel memory access usable for every refresh cycle. However, writing data into the refresh memory can require a separate memory cycle for every pixel of a vertical vector.
A vector generator may be produced which represents vectors at any angle as series of horizontal or vertical segments ("pixel runs") which are of uniform length and orientation for a given vector, except possibly the first and last segments of a vector. These segments may be produced by cycles of a vector/raster conversion device in a very short time (e.g., 70 ns per segment). However, conventional refresh memory organization would greatly degrade the speed advantages of such a technique for half of all the possible vector angles in a given implementation.
Vectors along the primary axis (usually horizontal) could be stored at the maximum rate permitted by the refresh memory; however, vectors between 45 and 135 degrees, or 225 and 315 degrees, would require a separate memory cycle for each pixel. Thus, parallel memory access would be of benefit in fewer than one-half of all possible vectors, and vertical vectors would operate at the lowest possible speed. Because most applications involve large numbers of vertical and horizontal vectors, this performance penalty can be very significant.
U.S. Pat. No. 4,559,611 assigned to the same assignee as the present invention deals with a memory mapping system having an adder for use with a raster scan memory refresh system. The system of this patent is adapted to writing vertical and horizontal vectors into the refresh memory so that no two adjacent vertical bits are written into the same memory chip. This patent has a comparatively high degree of computational complexity, however.
The system shown in the patent uses an adder to accomplish a memory reorganization by selectively changing address bits for vertical bits on writing into the memory. An adder is logically complicated and has a built in delay because of the need to wait for carry propagation. Thus, the use of an adder for a memory organization scheme is not as efficient as would be desirable for speeding up the vector writing function.
U.S. Pat. No. 4,500,928 also assigned to the same assignee as the present assignee, provides additional background information on display writing and refresh systems.
However, there remains a need for a display write and refresh memory system utilizing a high speed and efficient logic system with a comparatively low degree of computational complexity.